Here's some bit/bang stuff we wrote many many years ago to dump some stuff that had intentional clock jitter. Maybe give some ideas.
Code:
SaveA: equ $XX ;IO Register address
BTDelay: equ $F0 ;bit delay this can be any value ya like
;
;BootStrap code starts here
;
sei ;enable interrupts, not really necessary
lda #$55 ;55h is the response that basically says you are
;running this bootstrap, can be any value you like
bra Start ;run dumper
SendByte: sta SaveA
clra
bsr DecA ;Inter-Byte delay
ldx #$0A
coma ;invert byte
bclr0 $00 ;5 Zero Bit
bsr DelayBit ;1st Start Bit
bra SetIO ;3
SetIO: bset $00, #0 ;5 One Bit
bsr DelayBit
clc ;2nd Start Bit
SendBit: bcs Send1 ;3
bclr0 $00 ;5 Zero Bit |
bra bitdelay ;3 |count this for timing calc
Send1: bset $00, #0 ;5 One Bit |but not this
bra bitdelay ;3 |
bitdelay: bsr DelayBit
asla a ;3
decx ;3
bne SendBit ;3
bset $00, #0 ;Parity = 0, Stop bits = 1
rts ;6
DelayBit: ;standard 8 bit delay loop
sta SaveA
lda #BTDelay
DecA: deca
bne DecA
lda $XX ;SaveA This is the IO register
rts
Start: bsr SendByte
LongDelay: deca
bsr DelayBit
bne LongDelay
lda #$30 ;Start address of 3000
sta $47 ;Now address stored at 47,48 in ram
lda #$00
sta $48
; ---------------------------------------------------------------------------
dw $7180 ;Change page to eeprom
; ---------------------------------------------------------------------------
Loop: dw $92C6 ;Load A with the value of this next byte address 92C647
;Haven't fixed assembler to allow this new opcode yet
db $47
bsr SendByte
inc $48
bne Loop
inc $47
bne Loop
;need to create "reversible" idling loop here or rts
;
; | 1 STB | | 2 STB |
;
;I/O Pin >---------+ +--------+
; | | | ..... data bits
; +--------+ +--------+
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