ONe of the main routine[IRQ} on eside is triggered on each opti low res pulse, It doesn`t run without an active low res signal. That is still an assumption but it buggs the processor really hard. All other code is scheduled to run from some internal timers interrupts.

Eside have tons of free space. Using the last portion of the bin at FE00 will clear most of the patches from interference.

Tside is really short on free space. Some available addresses are $2004-$2014 , $3D33-$3D83, $FF84-$FF9F, These clears all the patches I have on tside so far.

If you came up with something I will be more than happy to test it.