Perhaps we have someone who knows DSPs well here?
My question relates to the patent I mention above in this thread. The execution unit has a block that is named "Immediate Data Generator. The second drawing details the execution unit and the arrows suggest that at times this block drives the A bus and/or the B_bus. Can anyone suggest the function of this block? My best guess (and only a guess) is that it supplies certain constants as directed by the microcode. Both P2A and T2B drive the block, there may be codes within the space (9 bits and 7 bits) that are used to deliver constants????
What would I give for just a data sheet!
-Tom
Small update:
Size of the Shared RAM is 128 X 16 which needs 7 address lines
Size of the Temporary RAM is 64 X 16 which needs 6 address lines
P2A is documented in the patent as having 9 address lines
T2B is documented as having 7 address lines.
I think the extra lines are used to address the immediate data generator when the requested data is not in the either of the shared RAMs.
Hmmmmmm, wonder if the immediate data generator is also in two ported ram. Earlier in this thread I was told that the same TIO chip is used in ABS systems. It would make sense to have as much as possible in RAM. I plan to look at the configuration routine again to see if there are indications that this is true.
-Tom
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