I continue to look at the "TPU" as it appears to be where most if not all of the time sensitive engine controls take place. I began by looking at it's initialization. The manner that it is initialized is the same in code for 1994 through 1997.

I believe the "TPU" is described in a Delco patent. Delco describes the part as a microprogrammed timer processor but throughout the text refer to it as TIO. You can view the patent at: https://www.lens.org/lens/patent/089-678-009-223-680 for confirmation the Patent Numbers: 5,115,513 and/or 5,117,387. They both look to me as the same idea...

The reason I believe this describes the part used in LT1 based vehicles is the description given in "PREFERRED EMBODIMENT" and "Architectural Overview" sections. The following is what I believe and will now seek to confirm. The following details suggest to me that the patent documents the 16195392 / TIO part.

- The size of the microcode store is the same between the patent and the TIO part. The given size is 256 words of 64 bits. The patent states: The microcode store is preferably in the form of a ROM although RAM or other memory technology can be used instead. The TIO uses RAM and configures it with the following sequence:

The microcode is loaded sequentially through four registers at $16E0, $16E2, $16E4, $16E6. Once four words are written, the destination microcode address is written to $1400. This initiates loading of the microcode word into RAM. The above loops through the 256 sixty-four bit words to complete loading the microcode.
The size of both the TIO shared RAM blocks exactly matches the patent. In the patent the combination of both blocks is referred to as "Parameter RAM" comprised of "Temporary RAM" and "Shared RAM". Patent sizes the shared RAM at 128 words by 16 bits and the temporary RAM at 64 words by 16 bits.

The code in the LT1 computers clears both shared and temporary RAM, the sizes match the patent exactly.


In reviewing the code, the patent, the application and what I know of the system, I come to the conclusion that the TIO is described by this patent.

I am most interested to hear if others agree or disagree and if anyone has found a match between the list of fields and the microcode loaded in the software. Here is the list of fields given in the patent:

P2A (9) Parameter to A bus
T2B (7) Temporary to B bus
SUB (1) Subtract/Add
SHC (2) Shift control
PWR (9) Parameter Write address
PWU (1) Write Unconditional
EXC (4) Execute (Branch) Condition
PNS (6) Pin/Flag Select
PAC (2) Pin Action Control
ENA/DIS (2) Enable/Disable
PRB (1) Present/Requested bit
REQ (6) Requested Address and/or Request Flag
DEC/END (2) Decrement/END Register
NAP (8) Next Address Pointer
NIP (4) Next Index Pointer

I am not sure which fields are assigned to which bits. I am trying to analyze that now.

Also there is the question of how the sequence of bytes the software loads are formed into words. Here is what I think:
Stated in the patent & makes sense from a 68HC11 point of view:

Byte0 Byte1:Byte0
Byte1
Byte2 Byte3:Byte 2
Byte3
Byte4 Byte5:Byte4
Byte5
Byte6 Byte7:Byte6
Byte7


This could result in the microcode loading into a 64bit word as:
Alternative 1 Byte7:Byte6:Byte5:Byte4:Byte3:Byte2:Byte1:Byte0

Should the design be consistant with writing high order first:
Alternative 2 Byte1:Byte0:Byte3:Byte2:Byte5:Byte4:Byte7:Byte6

Consider that the word high order first statement in the patent
doesn't apply to microcode loading:
Alternative 3 Byte0:Byte1:Byte2:Byte3:Byte4:Byte5:Byte6:Byte7


I have written a number of C classes to help with the analysis but as yet I can't determine the placement of fields within the microcode or the order that the byte sequence is loaded into the 64bit word. I will keep plugging away at this.

-Tom