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Thread: 16 bit address bus on P4 ECM's

  1. #1
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    16 bit address bus on P4 ECM's

    Trying to understand the 16 bit address bus on the P4 ECM. In a example address, 1111.0000.1111.0000, is A15 the leftmost and A0 the rightmost?

    Would $8000 be 1000.0000.0000.0000 and $FFFF be 1111.1111.1111.1111? Pin A15 on the EEPROM is hard wired to VCC, so that would be the first "1" in the previous addresses?

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    yes, A15 being the most significant bit will be furthest left. same for A0, least significant, furthest right.

    your 8000 and FFFF values are correct. windows calculator in scientific mode is helpful here, just input a hex value and switch over to binary and it displays as such.

    and A15 being permanantly connected to VCC is one of the more interesting things i've had to work around. i'm sure there are better ways to go about it, especially if one were to make their own MEMCAL adapter, but i simply removed the pin from the PCB, drilled a small hole through the side of the MEMCAL connector(on the PCM side), ran a pin through there, soldered a wire to it and on the other side of the wire i connected it to the A15 pin on the edgecard connector.
    1995 Chevrolet Monte Carlo LS 3100 + 4T60E


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    though the usefulness of that.... probably nothing, since as far as i know, the PROM won't be selected(via either PROMOE or PROMCS) when addresses under $8000 are selected. that's why i need to get my own MEMCAL adapter going with some logic gates on it to force the ROMOE and ROMCS signals to be active in locations that aren't occupied by internal registers or internal/external RAM.
    1995 Chevrolet Monte Carlo LS 3100 + 4T60E


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    Cool. In the process of forcing my brain around this stuff.

    Is there any reason you can think of that GM did not run A15 to the A15 pin on the EEPROM? Same effect in the end either way, just seems odd.

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    to screw with everybody attempting to modify the PCMs?

    i really don't know why they would have done such a thing, it limits what the engineers would have had access to if necessary.

    from what has been known about them for quite some time, GM had them custom built based on one of the early versions of the 6811, i think they may have specificed to motorola to have ROMOE and ROMCS be disabled when accessing anything other than the 8000-FFFF area. why they would have done this...... IDK.
    1995 Chevrolet Monte Carlo LS 3100 + 4T60E


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    What would be an effective means of testing out an address space (backed by NVRAM)? Blank it in a programmer, map it into the circuit, write data from the ECM, take it out and read it back on the programmer to verify? I would assume that if all the address you wrote to have data in them then it is a usable addres space?

    What happens if you have an overlap, such as mapping NVRAM to $1800-1fff and putting it in the 9396 ECM?

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    that is one way to test it. i would likely have it blank going in, have the ECM write to it, then spit out the location over ALDL with mode 2 or 3(i can't remember which). that's for single byte locations, if you were to write a large amount of data, definitely read out in the programmer and do a compare with tunerpro or something.

    and yes, i would assume if it is written to successfully and doesn't mysteriously change, it would work until the NVRAM battery dies in about a decade.

    overlap? problems, to say the least. i believe the proper term is "bus contention"? some unexpected and unpredictable things will happen.

    http://en.wikipedia.org/wiki/Bus_contention
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    These are the address ranges I was eyeballing, would give 15.5KB of address space. Now to figuring out the logic chips for the chip select.

    0200-03ff (overlap with some P4)
    0400-07ff
    0800-0fff
    1000-1fff (partial overlap with 9396)
    2000-2fff
    5000-5fff

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    those look simple to impliment. i would consider not using the 200-3FF range though... even in 1987(and possibly earlier) before GM released any ECMs that i know of that have 200-3FF RAM, they specifically avoided using it for HUD RAM... instead jumping directly into the 400 block. i get the feeling that they were playing with the idea if not prototypes that had RAM in that area. would have to open up the ECM and make sure that part number matches that of a known 00-1FF RAM P4.
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    more fun stuff: the P4 has elements of the P6 integrated into it. reason being, the earliest 68HC11s had a semi-multiplexed address and data bus. the first half of an instruction, 8 pins were used for an address(as outputs), then during the second half, they were switched to inputs to read data.

    the P4 also has a non multiplexed address and data bus, which first started with the 6811F1.
    1995 Chevrolet Monte Carlo LS 3100 + 4T60E


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    Starting to understand why the custom nature of the P4 68hc11 makes things difficult.

    Got the schematic to address all of the above addresses with the exception of 0200-03ff and just need to double check and get around to designing a PCB. Adding dip switches on the output side of the decoder chips could give an on/off for the address space in 512Byte chunks. I can imagine how it might proove useful to avoid overlaps but don't know enough about the various EMC's and the address spaces to know if it is needed or not aside from the 2k SRAM on the 9396.

    They got the NVRAM chips in a SMT package where the battery is replaceable and snaps onto the top of the chip (PowerCap Module). Anybody familiar enough with these to know how well they would survive the vibration of an engine compartment?

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    you can make your own nvram one guy on our forum makes these

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    have a link to those boards?

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    Thought of two ways to accomplish this.

    1. 7400 to control the write enable on the NVRAM, two or three decoder CMOS chips for the chip enable, and a couple quad OR gate chips to aggregate the chip enables. Looking at 6 chips to use the NVRAM for the extra address space and around 8 to use the NVRAM for the main 8000-FFFF in addition to the extra space. Then if you wanted to have an option to use EEPROM or NVRAM for the main 8000-FFFF space there would likely be another chip or two for the glue logic. ****design borrowed heavily from existing NVRAM products on the market****
    2. single microcontroller to handle all the glue, write enable, and chip selects.

    #1 is doable but would be interesting to do (and get to fit) with through-hole chips. #2 is simpler but everything would then depend on the reliability of the microcontroller and its programming. #2 would also allow for option selection without having to rely on DIP switches and/or jumpers.
    Last edited by brian89gp; 09-08-2013 at 11:02 PM.

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    Got the following ranges in the address blocks below drawn out in a diagram, needs a total of 7x 74 series chips which is doable by through-hole chips but SMT is probably the way to go. Each block would be able to be disabled/enabled by a DIP switch. I need to spend a while longer racking my brain to make sure I didn't overlook something, but it should allow for all address ranges to reside on the same EEPROM/NVSRAM.

    Now to test and hope that GM didn't leave some chips on the address bus only partially addressed.

    0200-03ff
    0400-05ff
    0600-07ff
    0500-0fff
    1000-1fff
    2000-2fff
    5000-5fff

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