pin changes for optical vs magnetic, but the way the code works, regardless of which is selected, either can get written to the RAM location that is used for MPH.

in this case, "optical" meaning if the VSS signal is basically the interface switching the signal to ground at a rate of 4000 pulses per mile. the ECM provides a current limited +12V via a 1.2K resistor, the U13 portion of the circuit is i think an inverter, but then it makes it's way to the U10(SCI Output) chip. there are a couple of logic gates there, eventually turns into "VSS", which goes to sheet#1.

magnetic works a bit differently. VSSHI goes into U24 which contains a zero crossing detector. when the voltage on that circuit rises above, then falls below 0 volts, the output of it toggles. you can see it branch down to the divider portion of the circuit, but it's not relevant so i'll skip past it. anyways, the signal makes its way to the U10 chip, where it runs through some logic(i think the first portion is a flip-flop?), but you can see that one of the outputs runs through more of the logic gates. anyways, there 3 AND and 1 OR gate in there. lets call the AND gates 1, 2 and 3 going from top to bottom. the logic works like this:

if optical VSS is selected: the signal simply runs through AND1, then into OR, where it becomes the VSS signal that the U2 chip creates the VSS period value for. U2 directly interfaces with U1, which is the processor. anyways, following the signal, it goes through U13 which inverts the signal(causing low to be high and high to be low). i imagine this is also done for voltage level matching(since 12V to some of these chips would probably kill them). then it goes to AND1. for an AND gate to go to logical 1, both inputs must be high. since the magnetic VSS signal will switch on it's own, let's look at the other input. it comes out of AND3, which has its state determined by "OUT4" and by a signal that comes from the limp-home hardware. OUT4 is controlled by the magnetic vs optical bit being set in the calibration. if it's not set toward optical, the AND3 causes it's output to change. note that AND2 inverts a signal, so it becomes active when AND1 is disabled.

so when optical is disabled, the magnetic signal is allowed to pass through AND2 and then OR.



it's kind of confusing unless you've dealt with logic gates before.