I forgot that you had found the transistor already...
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I wouldn't assume you can use any coil by simply driving it with a transistor. I'm pretty sure the GM ignition modules have current limiting, basically driving full-on until the current in the coil reaches the limit and then holding the limit.
Here's the coil schematic. Looks like it just needs a 5v signal
Attachment 12108
Not sure if you were talking to me or not. But I do know that the LS coils with the igniter built in are very basic. Hit one with a 5v signal and hold it. You will burn it out. Dwell time is controlled by the ECM. The pulsewidth of the 5v signal will prove it when you rev it up while watching it with an oscilloscope. It is not cost effective nor practical to install a dwell control circuit inside every coil. The size is a factor, not to mention temperature. More parts=more chances of failure. This is not a new concept for me at all. See it every day at work.
Now, you have to ask yourself.....do you want to pay $100 per coil or $45? Second, I will set up ion sense ignition feedback on mine, so I don't want any surprise circuitry in my way.
I have decided to use ordinary coils for mine, the rest can do as they will.
I'd pay about $25 for 8 from the junkyard assuming they'd work with the LT1 PCM. It's loaded with LS engines these days.
Sure, the LS coils are simple and the LS controls do dwell, but so what? The LT1 PCM isn't a LS PCM. I don't believe the LT1 ignition module is as basic. I have no idea if a LT1 PCM does any internal dwell timing or not but I doubt it. I expect the LT1 ignition module is a current limiting HEI type design. So, if you run the LT1/TBI etc coil on straight switched power you'll likely just burn it out.
I dont think we'll use an lt1 coil, i think the idea was to use the ls1 coil
I am not so sure the lt-1/vortec ignition module is auto dwell or not. Guess we'll find out. Not one of the most challenging problems ever, you know. You are putting cart before the horse. We need to get back to decoding and counting, otherwise we will get nowhere.
Here is a dwell calculator for you. Stretching the trigger signal from the ecm should pose no real problem.
http://www.useasydocs.com/theory/setdwell.htm
I will not discuss this any further until I need to. I have more important things to do. You have a better idea, draw it up and show us. That is why this forum exists. To share ideas and solve problems. Offer us something.
Getting a plan together first is better than going off half cocked with a "solution". But, you've got it all figured out so go ahead.
Still, this isn't your thread so it's not really your place to be pissy about my posts...
Personally, I will just buy a replacement sensor if it fails, or do a 24X conversion if I really want a change. So, I have no real incentive to design anything myself. I'd try to help but you apparently don't need it.
Still. thinking about it more I probably would have investigated using the combined rising or falling edges of the high and low res signals combined to clock a shift register chain of 8 flip-flops. Decode one of the pulse combinations to inject a 1 into the shift register each revolution. Then, the bit just passes through the chain at each TDC so there's you cylinder identification done and done. None of the AND gate decoding required and no latch required since the flip flops hold their state until the next low res signal comes along.
Here is how PCM interprets opti signal and what it counts.
High res signal is counted at every slot full or empty, totalling 720 counts.
Low res signal is trigger for high res counting. The cylinders are encoded 8 1 2 3 4 5 6 7 in the software.
The rotation could be backwards, not sure. TDC location on the disk is also not confirmed. Someone with dismantled opti could check rotor position and see where the disk is at #1 TDC.
All calculations in PCM are handled by a special third processor. Unfortunatelly I cant access rom section of the processor to make a dissasembly of the code.
If anyone knows how to read the third processor rom or have a dump of it, I will be more than happy to make a dissasembly.
Lionel, I did consider the method you mentioned above before I drew up the current design. It would work, but it would take as much as 2 crank rotations to sync, meanwhile the injectors are firing long before then, and might allow flooding in colder climates. I suppose you could disable the injectors until the sync, but I am uncomfortable doing so. So I decided to sync as soon as possible so that it won't change how the engine starts. This is simply a personal preference, nothing more.
Nice research, kur4o. I had posted previously an optispark wheel labled for coil switching and TDC. All leading edges of the Lo-Res signal indicate TDC. I had a spare optispark unit to confirm with rotor position, also. It is correct.
Looking at your picture, you can take make a decent guess that TDC will be the leading edge of each low res notch since the leading edges are all equally spaced 45* around the disk and it would only make sense for 1 edge of the low res signal to represent TDC.
It's also possible that the PCM detects the low res notch and then does the detecting to know the next upcoming cylinder so it can then fire that cylinder at the proper BTDC advance. So, the notch everyone assumes represents #1 TDC could really be to tell the PCM it's 45 notches from cylinder #8 being at TDC.
The LT1 never used a black block PCM. I'm quite positive the OBDII LT1 PCM was unique to that engine the same as the OBDI PCM was. You can swap between the OBDI and OBDII PCM's pretty much directly. Just the knock sensor changed and the OBDII had read O2's.
They sure look the same, and have the same wiring to them. But just in case, I have a smart ignition driver IC ready to intervene for the bargain price of $4.89 each.
http://www.mouser.com/ProductDetail/...klZFEN1w%3D%3D
It will come in handy for the future. I will order 8 of them in case. If not, I will use them in my bag of tricks at work used to save/convert old classic vehicles that intermittently show up.
The datasheet is available on that page.
Sorry about the delay, guys. Here's what I've got so far. not fully accurate, since I am missing a reset for the 4-bit counter, but it should get the idea across.
Attachment 12115
Hope this clears up any misinterpretation due to my horrible way of explaining things due to constant distraction. Nothing is set in stone, yet. The LOAD input on the 4 bit counter tells it to preset a value, and start counting from there with every LOW-RES leading edge. It is positive edge clocking.
This is the datasheet on the CD54ACT161 presettable 4-bit synchronous counter.
http://www.ti.com/lit/ds/symlink/cd74act161.pdf