Just discovered CPLDs and going to see if that will work.
Attached is the diagram. I think I got the 74HC00 wrong, the OE to the 74HC32 should be off of pin 6 and not where it is and the RW where the OE is.
Think combinding the ROMOE with the E and then the ROMCS with the CS with OR gates will work to use the same EEPROM/NVRAM for all of the addresses?
